DRAM Scaling Error Evaluation Model Using Various Retention Time

As process technology scales down, DRAMs become less reliable since current DRAM protection schemes cannot address scaling-induced errors effectively. In prior related work, faulty DRAM cells or inherent faults have been considered as permanent and easily detectable during manufacturing process. However, due to scaling, more errors occur intermittently during system operations and exacerbate DRAM reliability. To consider the increasing intermittent errors due to scaling, we propose a new error model using DRAM’s Variable Retention Time (VRT). Our model effectively describes latent inherent faults, which lead to intermittent errors, in addition to the permanent inherent faults. We also introduce an efficient methodology to accelerate simulations even with a myriad of inherent faults. We present parameter sweep results to provide better understanding or insight regarding DRAM scaling errors.