Simplified impedance design and control for low-cost high-speed channels

Impedance design is the fundamentals of signal integrity at the very beginning, but controlled impedance is always costly or time-consuming for the high-speed channels. In this paper, many simulations of channel parasitics were taken and calculated that met with the specified impedances and correlated to the measurements very well. Selection of the different substrate stack-up without any layout modification in the BGA package reversed from the failed verification to pass the differential return loss. Adjustment of lead widths and spaces in the limited room of leadframe package improved 6 Ω of differential-mode impedance compared to the conventional leadframe packages. The differential pairs with wider traces routed on the 2-layer PCB are more robust for over-etching effects whose impedance errors are less than 5% without special impedance control. Moreover, those pairs inserted with a thin ground trace achieved 90 Ω differential-mode impedance and 28.2 Ω common-mode impedance simultaneously with 35% less routing area for MHL application and reserved a 10 Ω series resistor for ESD protection. With those diligent designs, the leadframe package and the 2-layer PCB can be still adopting in the consumer electronics for high-speed applications.