Switching cell design with EMC and commutation losses criteria

This paper presents a MOSFET-diode switching cell model which is both accurate and fast allowing the designer to determine the optimum gate resistance in order to comply with both switching losses and EMC constraints. All technological parameters which are important in EMC studies such as parasitic inductance of layout and capacitive behaviour of semiconductor devices are taken into account. The model is implemented in MATLAB(R) that allows optimisation of the layout structure and derivation of parameters. As an application, the model is used in design procedure of a buck converter.