Modeling high current integrated power converters

This work presents an analytical model for integrated DC-DC converters at high currents. A loss model is constructed using parameters extracted from simulation or are available in the process manual and are scaled with the size of the device. The loss model is used to compare power converter implementations for varying on-chip size and power loss goals. Buck, 3-Level Buck, and Switched-Capacitor topologies are compared using this analytical model and then implemented in a commercial CMOS process. Validation of the constructed loss model is done through hardware measurements.