Silvaco based electro-thermal analysis of 4H-SiC TIV-JFET structure under extremely high current density resistive switching

A 2D model of a 1200 V normally-ON 4H-SİC Trenched and Implanted Vertical Junction Field Effect Transistor (TIV-JFET) cell structure was designed and simulated using Silvaco ATLAS TCAD software to investigate and understand the effects of extremely high current density pulsed switching on the device characteristics. The JFET cell was designed for an active area of 2 μm
²
and a threshold voltage of -7 V. Physics-based models were included to account for impact ionization, recombination effects, band gap narrowing, mobility and lattice heating. The electro-thermal simulation was performed using a resistive switching circuit at an ambient lattice temperature of 300 K. The circuit was designed for an ON-state drain current density of 5000 A/cm
²
. The device was simulated using a 100 kHz 50% duty cycle gate signal consisting of four switching cycles considering the simulation duration bottleneck. The analysis of lattice temperature profile revealed the formation of thermal hot spot in the channel area close to the gate P+ regions in the JFET structure. Further analysis showed an increase in the minority carrier concentration in the vicinity of the gate implants which affected the switching characteristics of the JFET at extremely high current density.