A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC

This paper presents a 2-GS/s 8-bit 16× time-interleaved (TI) analog-to-digital converter (ADC) for a millimeter-wave pulsed radar baseband system-on-chip (SoC). To suppress sampling timing errors among sub-ADCs, a foreground timing-skew calibration technique with small additional circuits is proposed. Measured spurious-free dynamic range and signal-to-noise distortion ratio at 1-GHz full Nyquist is, therefore, enhanced by 16 and 11 dB, respectively. Unlike conventional calibration techniques based on redundant ADCs or complicated digital calculations, additional circuit components are only several small resistors and a capacitor, resulting in only 0.4% area penalty. This area saving enables the compact integration of the radar baseband SoC with digital beamforming, where eight-channel TI-ADCs occupy the dominant chip area otherwise. Even though this is foreground, no system performance is sacrificed because the calibration sequence is closed loop and fast enough to be executed during an existing calibration interval in a periodic beam transmission sequence. The TI-ADCs are embedded on industrial SoC in a 40-nm CMOS process. The power consumption including the input buffer and the reference buffer is 54.2 mW from a 1.1-V supply, and figure of merit is 355 fJ/conversion step.