An FPGA-based Design of a Packetized Fronthaul Testbed with IEEE 1588 Clock Synchronization

This paper presents an architecture and an implementation of a field-programmable gate array (FPGA)-based Ethernet fronthaul testbed. The system exploits the IEEE 1588 precision time protocol for clock synchronization and is capable of transporting radio data from one baseband unit to two or more radio units, while allowing the evaluation of clock synchronization impacts on the actual radio-frequency signals. This work, then, focuses on its hardware setup and the adopted FPGA design. It emphasizes how the clocks recovered at the radio equipments are used both within their digital and analog domains, particularly for synchronization of the carrier frequency, sampling frequency and for steady occupancy levels at ingress elastic buffers. Some preliminary measurement results on synchronization performance are presented and show that the developed testbed is capable of achieving sufficiently high clock accuracy for packetized fronthaul investigations.