Networks-on-Chip With Double-Data-Rate Links

The need for higher throughput and lower communication latency in modern networks-on-chip (NoC) has led to low- and high-radix topologies that exploit the speed provided by on-chip wires-after appropriate wire engineering-to transfer flits over longer distances in a single clock cycle. In this paper, motivated by the same principle of fast link traversal, we propose the RapidLink NoC architecture, which exploits said speed to rapidly transfer flits between adjacent routers using double-data-rate (DDR) link traversals. RapidLink is enhanced with novel low-cost DDR elastic buffers that pipeline link traversal (when needed) to multiple flow-controlled half-cycle segments, whereby each segment is driven with data on both the positive and negative edges of the clock. DDR link traversal leads to multiple NoC configurations that can markedly increase network performance without increasing the area/power cost of the NoC relative to state-of-the-art single-data-rate architectures. Extensive cycle-accurate network simulations and hardware implementation results demonstrate the efficiency of RapidLink and its potential as a scalable NoC architecture.