A high-speed traffic manager architecture for flow-based networking

This paper presents a fast traffic manager architecture targeting to meet some requirements of the 5G next generation cellular communication technology, and of the high-speed networking devices in the software defined networking context. Also, an important goal is to reduce latency to a minimum in order to best support the upcoming 5G. The proposed traffic manager functionalities are policing, scheduling, shaping, and queuing of incoming traffic (packets) on egress ports in a network processing unit. Policing, scheduling, and shaping guarantee that packets are sent in such a way to meet the allowed bandwidth quotas for each flow, and enforce some desired quality of service. The implemented architecture is based on the C coding language and is synthesized with the Vivado High Level Synthesis tool. A throughput improvement of 2.0× over previous reported works is claimed. The proposed design of the traffic manager is capable of providing 15.8 Gbps per egress port for 64 byte sized packets, and it works at 93 MHz when implemented with a Zynq 7000 FPGA from Xilinx.