A 5GS/s 156MHz BW 70dB DR continuous-time sigma-delta modulator with time-interleaved reference data-weighted averaging

Conventional dynamic element matching limits the continuous time ΣΔ ADC architecture at high speeds. This work introduces a Time-Interleaved Reference Data-Weighted-Averaging (TI-RDWA) architecture that breaks the speed limitation of the traditional DEM decoder. Time-interleaving eliminates the reference voltage settling bottleneck, enabling DWA operation at 5 GHz, while still achieving the benefits of first order shaping of feedback DAC mismatch. The prototype 5GS/s ADC has 70dB and 84dB measured dynamic range and SFDR, respectively, in a 156MHz bandwidth. TI-RDWA improves SFDR by 17dB. The 40nm CMOS prototype consumes 233mW.