A 107 dB SFDR, 80 kS/s Nyquist-rate SAR ADC using a hybrid capacitive and incremental ΣΔ DAC

This paper introduces an architecture and design for high resolution, high linearity Nyquist rate SAR ADCs requiring only a single simple calibration at startup. The proposed architecture benefits from an intrinsically linear 1.5 bit ΣΔ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC. The ΣΔ DAC is also used for a single shot calibration of the coarse CDAC which therefore does not require good matching and can be sized solely upon noise requirements. A prototype was fabricated in 40 nm CMOS, with power supplies of 1.1 V and 2.5 V. It occupies an active area of only 0.074mm
²
. The prototype achieves a measured peak SFDR of 107 dB and a noise limited SNDR of 84.8 dB at 80 kS/s Nyquist rate operation. The core power consumption is 101 μW at 80 kS/s. In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5 kHz bandwidth.