A High-Performance Network-on-Chip Topology for Neuromorphic Architectures

Emerging neural network accelerators are often implemented as many-core chips and rely on a network-on-chip to handle the huge amount of inter-neuron traffic. The wellknown mesh and tree are the most popular topologies in prior many-core neural network accelerator designs. However, these conventional topologies suffer from high diameter, low bisection bandwidth, and poor collective communication support. In this paper, we present a customized version of the dragonfly topology for neural networks. The potential capability of dragonfly to support multicast and broadcast traffic in a simple and efficient way, as well as its low diameter, is the major motivation behind proposing a customized version of this topology as the communication infrastructure of neural network accelerators. We compare dragonfly with some state-of-the-art NoC topologies adopted in recent neural network hardware accelerators and show that dragonfly yields lower average message hop count and higher throughput that translates to faster neural information processing.