Automated software-based self-test generation for microprocessors

Software-based self-testing (SBST) is a well-known non-intrusive method for testing microprocessors. This paper presents a tool for automated Software-Based Self-Test program generation. The tool is based on the previously published methodology of using High-Level Decision Diagrams (HLDD) for modeling microprocessors and faults. The tool generates from the Instruction Set Architecture of the processor its HLDD model and using the formalism of the HLDD model, together with beforehand prepared code templates, generates the final self-test program. The functionality of the tool is demonstrated by carrying out experimental research on test generation for the 8-bit microprocessor PARWAN and the 32-bit SPARCv8 microprocessor Leon 3. In combination with the fault simulation tools, it is a novel solution for SBST program generation. The experimental results demonstrate the advantages of the implemented method in comparison with previously published results.