Exploring DDR4 Address Bus Design for High Speed Memory Interface

This paper discusses multi-point address channel design in fly-by topology for high speed memory interface. Waveform behaviors at DRAM locations along the channel are examined in depth with eye opening data in various channel design factors and device termination settings. Eye opening is exacerbated on the front DRAM from the controller more prominently due to ring-backs from high frequency reflections at the node while eye opening at DRAMs along mid-channel is more notably affected by dual eye tracks from effective channel impedance to termination mismatch as well as high frequency loss from DRAM nodes of channel front. Channel design is explored for overall channel performance improvement to consider different waveform behaviors at address input nodes of multiple DRAMs along the channel and design suggestions are developed.