Ga Liquid Metal Embrittlement for Fine Pitch Interconnect Rework

Heterogeneous integration is considered to be essential to maximal exploitation of the densification, performance and system cost potential of semiconductor packaging. To ensure high yields of these multiple device systems without sacrificing packaging integrity and reliability, a rework process that can effectively and locally remove defective chips is a sought-after element. Motivated by chip removal challenges on fine pitch interconnects with low volumes of Pb-free solder and relatively high intermetallic content, a novel method of die separation that minimizes the need for high heat is proposed and validated. The approach exploits a known failure mechanism for metal systems known as Liquid Metal Embrittlement (LME) to weaken chip level interconnects and facilitate separation. Specifically, this work investigated the use of liquid Gallium (Ga) to effect SAC solder interconnect embrittlement. To study the LME effect, SAC BGA samples were exposed to liquid Ga. Subsequent shear force testing demonstrated the embrittlement phenomenon and showed a dependence on exposure time and temperature as well as surface coverage. Characterization of specimens at various stages of liquid Ga exposure proposes an embrittlement mechanism that comprises both intergranular and transgranular diffusion as exhibited by the progressive creation of multiple grain-like structures defined by the liquid Ga penetration. To enable practical application in flip chip rework processes, a number of means were explored to promote liquid Ga infiltration into the chip to substrate gap. The most effective approach, using liquid Ga micro particles dispersed and suspended in a flux solution, resulted in a solder exposure that enabled some degree of embrittlement with interface separation predominantly within the solder and efficient removal of excess liquid Ga. These results recommend further work to optimize the size and concentration of liquid Ga in the suspension in order to improve exposure conditions and accelerate embrittlement, followed by chip replacement tests to validate wetting and reliability of the newly formed interconnects.