Reflow Warpage Induced Interconnect Gaps between Package/PCB and PoP Top/Bottom Packages

Package warping during SMT reflow is a serious concern as warpage induced interconnect failures such as Head-in-Pillow (HiP) and Non-Wet-Open (NWO) must be controlled. In this study, the high temperature reflow dynamic warpage characteristics of BGA packages are examine during simple, controlled gap between the solder ball and printed paste interconnect to simulate separation and lifting of the joint due to package warping. By measuringthe in-situ gaps during reflow, the threshold gap valuethat will result in failures is determined. The controlledgap experimental may also be applied to investigatemaximum warpage allowed for the top PoP memorypackage in a PoP stack assembly. The experimental set up and procedures aredescribed in detail. Actual SMT failure results are usedto compare the threshold gap values that suggest failurecould occur. Based on the correlation, it is possible tobacktrack the interconnect gap values to maximumpackage warpage limits as used in industry standards forhigh temperature flatness requirements for BGA packages.