GaN vertical nanowire and fin power MISFETs

GaN vertical power devices have many advantage over lateral device in device scaling, reliability and thermal management, etc. Traditional power transistors employ p-type pockets to achieve E-mode, RESURF and avalanche capabilities. However, this topology in GaN vertical power transistors has been challenging to implement [1] due to the difficulty to achieve selective area doping without compromising breakdown: p-type pockets in n-type regions or vice versa. The GaN UMOS-FETs or trench MOSFETs can be realized using epitaxial p-layers, however, suffer from low channel mobility in the inversion channel [2, 3]. Using n-type GaN only, depletion mode vertical MISFETs can be achieved with attractive current densities and breakdown voltages [4]. To get normally-off operation, Fin or nanowire (NW) pillars are necessary geometries. Compared with Fins, GaN nanowires have added advantages including superior electrostatic control and possibility for low-cost growth on foreign substrates [5, 6]. In this work, we report the first experimental demonstration of NW-MISFETs on bulk GaN substrates and compare them with Fin-MISFETs with the state-of-the-art performance fabricated on the same sample. The benefit of better electrostatic gate control in nanowire MISFETs are highlighted.