Reduction of interface states in Ge/High-k gate stacks and its reliability implications

This work reviews a process that was developed to enhance the interface state density of a Ge/High-k interface. A slot plane antenna plasma oxidation (SPAO) process was implemented during dielectric deposition steps to fabricate TiN/ZrO
₂
/Al
₂
O
₃
/p-Ge MOS gate stacks. A poor interface was observed with SPAO being performed before Al
₂
O
₃
/ZrO
₂
gate stack deposition because of fragmented GeOX interfacial layer formation. Significant decrease in interface state density was observed because of the formation of a stable and moderately thick GeOX interfacial layer when SPAO was performed in between Al
₂
O
₃
/ZrO
₂
deposition. When SPAO was performed after the deposition of both the high-k layers, higher Dit was observed suggesting a GeO
₂
layer formation. Time Dependent Dielectric Breakdown (TDDB) measurements suggest that stable and moderately thick GeOX interfacial layer (SPAO was in-between the two high-k layers) provides better immunity to degradation under stress. It was further observed that if GeO
₂
is at the interface then it degrades at a faster rate. The trap distribution in dielectric layers and interfacial layer properties contribute to the dielectric breakdown. SPAO seems to be an excellent processing step during high-k deposition to enhance the Ge/High-k devices.