A 12-bit 250MSPS Pipeline ADC with 4Gbps serial output interface

A 12-bit 250MSPS Pipeline ADC with serial output interface is presented. The pseudo random (PN) calibration technique is used to improve the dynamic performance in the high speed ADC. A integrated serial output interface is implemented to convert 12 bit parallel data into a differential serial data stream. The whole pipeline ADC was fabricated in 180nm 1.8 V 1P5M CMOS process. Test results show that the ADC can achieve SNR of 69.92dB and SFDR of 81.17dB with 20MHz input signal at full sampling speed. The active ADC with the serial output interface consumes a power consumption of 395mW and occupies an area of 2.5*3.2mm2, where the active area of the interface is 0.5*1.5mm2.