A 450-Mb/s analog front end for PRML read channels

A 450-Mbit/s analog front end, integrated into a 16/17 code rate EPR4 read channel for hard disk drives, uses an automatic gain control (AGC) circuit with digital feedback. Multilevel qualification and a variable loop time constant enable the AGC to acquire a 12-dB gain change within 5 data bytes. The front-end circuitry incorporates a programmable gain amplifier (PGA), an exponential variable gain multiplier (VGA), a seventh-order 0.05/spl deg/ equiripple linear phase 20-120-MHz low-pass filter with 0-15-dB high-frequency boost, and active ac coupling. The PGA and VCA combine to give a 48-dB gain range with a 500 MHz -1-dB bandwidth for a power supply of 3 V. The embodiment of thermal asperity and amplitude asymmetry compensation circuitry makes the analog front end ideally suited for applications using magnetoresistive read heads. Implemented in a 5-/3.3-V dual-voltage .35-/spl mu/m BiCMOS process with a gate-oxide thickness of 75 nm and 16-GHz npn F/sub T/, the complete circuit occupies 2.29 mm/sup 2/ and dissipates 232 mW.