TSV-to-TSV crosstalk induced delay analysis for 3D ICs

TSV (Through-silicon Via) meets the demands of high speed and low power consumption in 3D integrated circuits. However it faces challenge in signal integrity problem such as crosstalk. TSV to TSV coupling is the most significant crosstalk problem in TSV based 3D ICs. This paper presents a quantitative estimation on the TSV to TSV crosstalk induced interconnect delay, trying to find the worst interconnect delay and increase circuit crosstalk tolerance. We simplifies the existing TSV to TSV crosstalk model with TSV parasitic parameters. This model is validated by finite element simulation tool. Using this model, we calculate output signal voltage response and crosstalk signal voltage response. Adding these voltage response together, time continuous output signal voltage equation can be obtained. From this equation, we can easily calculate the circuit delay. The simulation result shows that interconnect delay increases at most 85.73% because of TSV to TSV coupling, which cannot be negligible in static timing analysis (STA). Our simulation result is reliable since it has only 5.3% deviation compared to Spice simulation result. And our method is faster than Spice simulation theoretically.