EMC-oriented design of output stage of synchronous buck converter

Electromagnetic interference generated by synchronous buck converters may violate the limits specified in the regulations. A design of the output stage of synchronous buck converters in which two pairs of the high-side (HS) and low-side (LS) field effect transistors (FETs) are placed in a LS-HS-HS-LS configuration is proposed. Two converters with the discrete components are designed to evaluate the proposed configuration. The measurements performed by a transverse electromagnetic (TEM) cell show that the converter with the proposed configuration generates significantly smaller radiated fields than the converter with the conventional configuration of the output stage.