Radiation-Hardened CMOS Negative Voltage Reference for Aerospace Application

Voltage reference is the key module in analog and mixed-signal integrated circuits. This paper presents a radiation-hardened CMOS negative voltage reference for aerospace electronics. To improve the antiradiation performance, in the circuit design, the input pair of the operational amplifier is replaced from pMOS to nMOS. An extra unity-gain amplification stage is added and the compensation network is optimized. Besides, the start-up circuit is redesigned. In the layout design, the annular-gate structure is adopted to eliminate electric leakage, while the layout technique against single-event latch-up is also used. The prototype of the proposed circuit is fabricated using a bulk CMOS 0.6-μm process with a 547 μm × 618 μm chip area. By using the proposed circuit and layout optimizations, the measured temperature coefficient of reference is reduced to 13 ppm/°C and the output voltage drift is below 1.2% after 300-krad(Si) total ionizing dose. The measured single-event latch-up threshold is above 94.6 MeVcm
²
/mg.