Monotonic static CMOS and dual V/sub T/ technology

We developed a methodology and tools for synthesizing monotonic static CMOS networks, which consist of alternating low-skewed and high-skewed static gates. When used with a dual V/sub T/ process, monotonic static CMOS can simultaneously reduce standby static power and increase performance by using low V/sub T/ devices in the evaluation networks and making all other devices high V/sub T/. Experimental results show monotonic static CMOS to be 1.67 times faster than traditional static CMOS.