A 0.22 /spl mu/m CMOS-SOI technology with a Cu BEOL

A 0.22 /spl mu/m CMOS on SOI technology, using a nonfully depleted device, is developed. This technology uses the same gate lithography and metallization as a comparable bulk technology, but offers a 20-35% higher performance at the chip level. Furthermore, it offers the complete device and circuit elements used in bulk CMOS (low V/sub T/ device, ESD diode, and decoupling capacitance). This technology was applied to a 64 b RISC processor.