Chip package interaction with Cu Pillar interconnects - systematic study of key factors impacting the qualification

Advanced silicon technology nodes are using backend of line (BEOL) stacks consisting of ultra low-k (ULK) materials. ULK materials in combination with Flip Chip (FC) packages and Cu pillar first level interconnects require a chip package interaction (CPI) characterization strategy. Package level tests are needed to account for the thermal mismatch or warpage induced stress between the silicon die and the polymer substrate. The work described here focuses on the impact of the BEOL metal fill and BEOL design rules (Figure 1). Since the evaluation with multiple reflow (MR) test data was proven to be suitable for an early CPI risk assessment and the correlation to standard reliability tests was shown in previous work [1], the same test vehicle (TV) with respect to die size, BEOL metal stack and test condition was used. The test vehicle was successfully re-designed to accommodate three significant different BEOL metal densities in the two uppermost ULK layers. These levels of metal density cover the typical product range and an extended engineering level for an understanding of the margin. This study allows GLOBALFOUNDRIES to build a consistent and broad data base to judge the actual densities in product designs and their criticality. The collected data proved the working hypothesis that a decrease of the metal density will increase the failure rate in engineering stresses beyond the qualification requirements. In scanning acoustic microscopy (CSAM) analysis BEOL delamination in the die corners were detected and confirmed using FIB cut cross sections. Strategies for strengthening the BEOL by process parameters adjustments were confirmed.