Novel parasitic-SCR impacts on ESD robustness in the 60 V power pLDMOS devices

The pLDMOS related devices fabricated by a TSMC 0.25 μm 60 V process was investigated in this paper. For the ESD improvement, some DUTs inserting the N
⁺
zone to form an embedded SCR in the drain end or guard-ring area, respectively. From the TLP testing results, the I
_t2
values of the drain parasitic SCR npn-type and pnp-type could reach > 7 A, higher than that of the traditional pLDMOS device. However, the V
_t1
and V
_h
values of the pLDMOS-SCR npn-type were less than that of the pnp-type. Furthermore, the V
_h
value of the pLDMOS-SCR (ring pn-type) was higher than that of the pLDMOS-SCR (ring pn-type_Del co) for the high immunity of latch-up effect. The I
_t2
capability of pLDMOS-SCR (ring pn-type) can reach 3.223 A, then as compared with the traditional pLDMOS increased about 251.8%. Therefore, the pLDMOS-SCR (ring pn-type) is a nice layout manner for the ESD robustness and anti-latch-up immunity.