Evaluation and reduction of charging damage during metal etching

In order to evaluate and find ways to reduce charging damage during metal interconnect etching, a circuit model including electron cyclotron resonance (ECR) plasma, devices on the wafer and bias power source is developed. As the interlayer dielectric thickness increases and capacitance decreases, AC stress current during main etching must be taken into account. The macroscopic charging due to peripheral etching can be reduced by lowering the bias frequency and magnetic field strength on the wafer. The microscopic charging caused by electron shading is expressed by this circuit model and its reduction by time modulation (TM) biasing is shown.