NVMLearn: A simulation platform for non-volatile-memory-based deep learning hardware

Hardware implementation of deep machine learning using the convolutional neural network has been successfully demonstrated using array architecture with non-volatile storage elements such as floating-gate MOS transistor, resistive memory, phase change memory, etc. We present a new simulation platform, NVMLearn, to aid the design, verification, and system-level power and performance estimation for such architecture. Physical characteristics of memory devices are modeled using Verilog-A compact models, which can be easily simulated in SPICE to obtain the device programming, erasure, and read behavior. On the system level, NVMLearn simulates the training of the entire convolutional network based on any non-volatile memory device type.