ESD-reliability influence on LV/HV MOSFET devices by different zapping-voltage steps in the transmission-line pulse testing

Impacts of zapping-voltage step (ΔV) setting on the final fault-diagnostic measurement of transmission-line pulse (TLP) testing are presented in this paper. In order to identify the influence on electrostatic-discharge (ESD) immunity evaluation, three kinds of MOSFET devices are employed, which are the LV nMOSFET (0.6-μm/5-V), HV nMOSFET and HV pMOSFET (1.8-μm/12-V) technologies devices, respectively. After a series of systematic TLP measurement, it can be found that the above mentioned variable (ΔV) has a very serious repercussion on the I
_t2
-value decision of LV nMOSFET and HV nMOSFET (the deviation caused by a maximum ΔV was up to 13.6% in the LV nMOSFET DUT, 185.4% in the HV nMOSFET DUT as compared with the corresponding Reference ΔV group), but the impact on HV pMOSFET DUTs is very weak about 0.14%. Therefore, in order to get a true I
_t2
data of DUTs, the zapping-voltage step (ΔV) setting during the TLP testing should not too small.