A practice of 2-to-2 fixed priority arbiter used to multi-core processors

Bus is the main communication channel for processor from/to memory or external devices to deliver data or commands. Advancement, if the jobs are co-executed by the processor with multi-cores, the bus management is very important and to be depended by the arbitration strategy. In this paper, the system-on-chip insides two DLX processors, which has 32 bits and are implemented by the ARM SoC Designer simulation tools. For convenience controlling the traffic scheme among cores, we accomplished a 2-to-2 fixed priority arbiter to inside the issued multi-core. Through the bus race emulation, we obviously obtain the result while the duty is increasing, but the bus collusion not obviously grown. The result is very valid and refers to the multi-cores design.