Plasma process induced degradation of thin inter-polysilicon dielectric layers

In this work, we report details of plasma processing induced damage to thin (3 to 10 nm) silicon dioxide (SiO/sub 2/) and oxide/nitride/oxide (ONO) layers formed on polysilicon by rapid thermal processing (RTP). The observations were made during process development of a planar polysilicon/insulator/polysilicon capacitor structure. The aim of the work was to develop a planar capacitor structure with a capacitance per unit area in the region 5 to 10 fF//spl mu/m/sup 2/, and integrate the capacitor module into a BiCMOS process. During the development work, a number of observations were made relating to plasma damage to the thin inter-polysilicon dielectric layer. It was observed that the dielectric type (ONO or SiO/sub 2/), and the method used to contact the polysilicon 2 layer of the capacitor structure, had a pronounced effect on the susceptibility of the thin dielectric layer to subsequent plasma processing damage. The results presented in this work are relevant to the development of polysilicon-insulator-polysilicon structures in a range of applications, such as DRAM and EEPROM cells, double polysilicon capacitors in analog applications and to the integration of high value on-chip capacitors.