Improving the low-frequency noise performance of input/output DRAM peripheral pMOSFETs

The low-frequency noise behavior in linear operation of input-output (I/O) pMOSFETs for Dynamic Random Access Memory (DRAM) applications is studied for different process conditions: the 5 nm SiO
₂
/2 nm HfO
₂
/TiN stack is compared with a wafer subjected to a post-deposition SF
₆
plasma treatment and with a split where TiN is replaced by a TaN metal gate. It is shown that while the variability in the noise power spectral density is higher for the latter two cases, the low-noise devices exhibiting predominantly 1/f noise give rise to a one decade smaller oxide trap density. It is shown that potentially, the same noise performance as for standard SiO
₂
/polycrystalline Si gate I/O transistors can be achieved by the studied alternative process conditions.