Calibration of Bulk Trap-Assisted Tunneling and Shockley–Read–Hall Currents and Impact on InGaAs Tunnel-FETs

The tunnel-FET (TFET) is a promising candidate for future low-power logic applications, because it enables a sub-60-mV/decadesubthresholdswing. However, themost experimental TFETs are plagued by unwanted trap-assisted tunneling (TAT) and Shockley-Read-Hall (SRH) carrier generation, which degrade the swing and increase the leakage floor, hence forming a major roadblock for TFET adoption. This degradation is attributed to bulk traps, semiconductor/oxideinterface traps, and/or heterojunction interface traps, but it is still unclear which of the three trap types are dominant. In this paper, we focus on TAT and SRH caused by bulk traps. We calibrate SRH and TAT models with the help of In
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Ga
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As p+/n+ and p+/i/n+ diodes grown on lattice matched substrates by molecular beam epitaxy (MBE). We then perform calibrated simulations of an In
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Ga
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As TFET, which show bulk SRH and TAT are sufficiently low compared with the target OFF-state current and, hence, not a significant issue. Therefore, it is likely that high SRH and TAT commonly observed in experimental homojunction InGaAs TFETs, MBE-grown on lattice matched substrates, are not caused by bulk semiconductor defects, but by semiconductor/oxide interface defects.