Systematic and random defect reduction during the evolution of integrated circuit technology

As integrated circuit technology continues its historic progression down the road to ever diminishing feature size, device yield inhibitors due to systematic and random defects play an increasingly critical role in controlling the rates of technology learning and yield ramping. This paper presents a variety of new methods for facilitating random and systematic defect learning during the development of 0.18-0.25 micron Logic technology, emphasizing four principal activities - predicting random defect limited yield, improving process tool particle control, addressing systematic limited yield, and optimizing in-line defect inspections applied to both product and short flow monitors.