Automated generation of system-level AMS operating condition checks: Your model's insurance policy

Analog/Mixed-Signal (AMS) design and verification strongly relies on more or less abstract models to make extensive simulations feasible. Maintaining consistent behavior between system model and implementation is crucial for a correct verification. Operating conditions have to be a major concern: A faulty model might introduce false-positive verification results despite of erroneous operating conditions. We propose a novel method to automatically generate a model safe-guard unit from transistor-level simulation data. We introduce this unit into an abstract model in VerilogAMS to check the validity of the current operating conditions. This method can be used to significantly reduce the risk of erroneous verification results on system level. We demonstrate our approach using an RFID demodulator circuit. The model is automatically augmented with additional checks derived from an exploration of the underlying circuits' parameter space. By comparing the risk of false-positive simulation results, we prove that the design risk can be nearly eliminated.