DDR3: Bridging emulation to validation

Today every SOC design company is emphasizing on a process which can ensure healthy silicon at first tape-out and that too, with as less time-to-market as possible. For this, various methodologies are getting derived to catch most of the corner cases of the design before silicon is fabricated. Pre-silicon emulation has come into existence for the very same purpose. Even if SOC verification guarantees controllability, observabilty and reproducibility of a bug (if any in DDR3) in its environment, it is limited by the high simulation time. Therefore, breadth and depth of coverage in its environment is still a challenge and that's where pre-silicon emulation comes into picture to address such issues. Pre-silicon emulation of DDR3 is used to catch and fix the bug before tape-out which has escaped IP and SOC verification. Faster emulation time and closer to the actual silicon environment makes it more meaningful and standard choice of the semiconductor industry. This paper describes the challenges faced while Pre-silicon validation of DDR3 and system level scenarios generated in pre silicon environment in order to have confidence in silicon beforehand. It also elaborates on performance part of DDR3 which talks about the DDR profiling based on its configuration.