VLSI thermal placement issues: A cooperative game theory based approach

In this paper we address the issue of the thermal placement problem for gate arrays in VLSI physical design. With the steep rise in the compaction density and the power consumption in the System-on-Chip (SoC) has necessitated the minimization of heating in the chip level. Random distribution of temperature may create discrete hotspots. These may have adverse effect on the reliability issues, timing failures, delays and other related parameters etc. To resolve this problem, we considered matrix synthesis problem (MSP) formulation for VLSI standard cell placement. A coordination game based algorithm has been developed to minimize the heat generated locally (hotspots) on chip. In this paper, we have presented a game theory based technique for handling the thermal placement issues in VLSI design automation. The proposed method has been tested using simulations on randomly distributed layout models and the results are found to be quite encouraging.