Design and implementation of 4096 point FFT for satellite communication

FFT is one of the essential tools used in applications such as video processing, image processing and multi carrier systems. But due to its intensive operation, it takes more area along with increased power consumption. Hence, a hardware efficient FFT algorithm is a prime requirement. After a survey of various FFT algorithms, because of its pipeline architecture Radix-2² SDF algorithm is chosen as the optimum hardware efficient FFT algorithm. Since the resolution increases with increase in number of samples, a length of 4096 is preferred for the acquisition system (one of the applications of FFT for satellite communication). The system level simulation is performed using MATLAB-Simulink. The algorithm is simulated using HDL programming language. The simulated HDL code is validated using Xilinx ISE synthesizer using Virtex-4 FPGA (XC4VSX35-10FF668). The real time testing of the algorithm is performed with an OFDM system. With inputs of 8 bit, it was found that an accuracy of 99.86% can be obtained. Also for 4096 points, the hardware consumed was 81%. Which implies the algorithm used favors hardware efficiency.