Gate oxide yield improvement for 0.18μm power semiconductor devices with deep trenches: DP: Discrete and power devices

Two unique gate oxide failure mechanisms are associated with deep trench processes for a 0.18 μm power semiconductor device. One failure mode is a “mini-LOCOS” defect, that is due to inadvertent oxidation of Si in the active area during deep trench oxidation. The other failure mode is due to slip associated with dislocations from the deep trenches. These defects are eliminated by optimizing the SiN oxidation barrier used during deep trench oxidation and by optimizing high temperature anneals to minimize dislocation generation.