Defect improvement by optimizing electroplating in BEOL sub-50nm pitch

Electroplating for the sub-50 nm pitch back-end-of-line (BEOL) interconnect metallization has become increasingly challenging mostly because of marginal seed coverage, inadequate plating process and/or chemistry, the limitation of scaling the barrier-liner and seed thickness. In this study we show how inadequate plating due to the marginal seed caused degraded via open yield along the perimeter of wafers from the 9:00 to 3:00 o'clock position which we termed as a “crown”. The analysis of a failed die by transmission electron microscope (TEM) revealed that a systematic embedded via void had caused such open yield degradation at the “crown” area. Plating waveforms were used to mitigate via voids through enhanced conformal copper nucleation and void free fill. The optimal plating waveform repeatedly demonstrated virtually equivalent via open yield between crown and non-crown (remaining area of the wafer) areas without any yield degradation at crown. We have shown that the overall via open yield was improved by ∼ 25% over the base-line best known method (BKM).