Modeling of tone inversion process flow for N5 interconnect to characterize block tip to tip

Tip to Tip (T2T) of interconnect lines in advanced CMOS is quite important when downscaling the area of SRAM and logic standard cells. When T2T size is increasing we have less space for via placement. Additionally variability could impact the yield of the Dual Damascene (DD) structure because of via placement or alignment. As we continue to extend 193i lithography for patterning block using multi-patterning schemes, it is important to understand which processes have the most impact to T2T variability. In this paper we characterize the process window of key steps in a multi-patterning flow using Tone Inversion (TI) by studying the factors affecting CD in a T2T construct with 193i. We run a quantitative process window study of TI flow by using a DOE with emphasis on evolution of T2T dimension all completed on a virtual platform using COVENTOR SEMulator3D® tool. The virtual results were compared with 300mm silicon data processed at IMEC site with good agreement.