Linear P-top technology for 600-800 V ultra high voltage BCD integration process

A 600-800 V, BCD technology platform is presented in ultra-high voltage applications. An innovative feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an epitaxial or a buried layer. Ultra-high voltage triple RESURF LDMOS with the breakdown voltage up to 600-800V as well as low voltage CMOS and BJT have been achieved using this BCD process. An economical manufacturing process, requiring less masking steps, yields a broad range of MOS and bipolar components integrated on a common substrate, including 600-800 V nLDMOS, bipolar and low voltage devices. With the process simulator TSUPREM4 and 2D device simulator MEDICI a robust triple RESURF nLDMOS with a 10% Process variation of P-top dose maintain breakdown voltage with low specific on-resistance and maintain lower source Electric field with good IV Performance is successfully optimized and realized. The results of this technology is low fabrication cost, simple process and for switching power supply applications.