ESD-immunity evaluations of a 40 V nLDMOS with embedded SCRs in the drain side

The impacts of current-path variation on the ESD robustness of nLDMOS devices as the drain-side modulation by a 0.18 μm/40 V process are evaluated in this paper. From the transmission-line-pulsing (TLP) measurement, the secondary breakdown current (I
_t2
) of an nLDMOS with the drain-side embedded SCR structure & "pnp" arrangement (DUT-2) increased from 2.498 A up to > 7 A (at least upgraded 180%) as compared with the reference nLDMOS device. And, the trigger voltage (V
_t1
) is also decreased; particularly the reduction of the pure SCR (DUT-3) is the most one. Meanwhile, the Ron of the pure LDMOS (DUT-4) increased, and the I
_t2
value can also upgrade from 2.498 A to 3.043 A (improved about 21.8%). In this paper, we can find that the I
_t2
value of the Reference nLDMOS is lower than that of the pure SCR and pure nLDMOS translated from the nLDMOS-SCR (pnp-arranged); therefore the I
_t2
value of this nLDMOS-SCR (pnp) composed device will be higher than the Reference nLDMOS.