Automatic testing of analog ICs for latent defects using topology modification

An automatic, defect-oriented method is proposed for activating latent defects in analog and mixed-signal integrated circuits. Based on the topology modification technique, added stress transistors generate voltage stress that activates these latent defects. This contrasts with burn-in testing which uses increased temperatures as a fault activation mechanism. Moreover, this Design-for-Testability algorithm gives the trade-off between fault activation rate, silicon area cost and testing time for different test solutions. Both CMOS and DMOS devices are handled to accommodate the testing of high-voltage circuits. When applied to latent gate oxide defects in a voltage regulator circuit, an activation rate of up to 76.7% is achieved. In comparison, the stressing by increased supply voltage only reaches 28%. For the same testing time, this improvement comes at the expense of three additional stress transistors with a silicon area overhead of less than 1%.