On Bit-Serial NoCs for FPGAs

We can build lightweight bit-serial FPGA NoC routers that cost 20 LUT, 17 FF per router and operate at 800-900 MHz speeds. Each bit-serial router implements deflection-routing on a unidirectional torus topology requiring lb-wide connection per port. The key ideas that enable this implementation are (1) reformulation of the dimension-ordered routing (DOR) function using compact 1 LUT, 1 FF streaming pattern matchers, (2) compact retiming of the datapath signals into SRL16 blocks, and (3) careful FPGA layout to efficiently pack the router logic into small rectangular regions 2 × 4 SLICES on the chip. We anticipate these bit-serial NoCs can be used in a variety of scenarios including overlay support for triggered debug, lightweight control signal dissemination, massively-parallel bit-serial processing.