A novel structure of silicon field emission cathode with sputtered TiW for gate electrode and TEOS oxide for gate dielectric

A novel silicon field emission cathode structure with a narrow spacing between tip and gate electrode is proposed, based on the filling characteristics of the sputtered Ti/sub 0.1/W/sub 0.9/ beneath the disc-shaped tip-mask oxide. Without advanced lithography technologies, the hole diameter of the gate is reduced to a sub-half-micrometer of /spl sim/0.4 /spl mu/m from an initial tip-mask size of /spl sim/1.2 /spl mu/m, and the gate electrode easily approaches the cathode, leading to a low-voltage operation. A uniform and stable field emission cathode is obtained using well-established VLSI process technologies. The current-voltage (I-V) characteristics of the cathodes show low turn-on voltages of /spl sim/30 V.