Silicon tunnel FET with average subthreshold slope of 55mV/dec at low drain currents

In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. It is shown that the device achieves I
_on
/I
_off
ratio of 5×10
⁴
considering I
_on
(V
_on
= V
_Ioff
-0.5V) = 0.8×10
^-8
μA/μm and an average SS of 55mV/dec over two orders of magnitude of I
_d
. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency g
_m
/I
_d
beats the MOSFET performance at lower currents.