Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs

In this paper a compact model for intrinsic capacitances for Tunnel field-effect transistors (TFETs) is presented. The model is derived from the carrier concentration and current flowing the channel of a Si Double-Gate (DG) n-type TFET. It represents a particularly good estimation of TFET capacitances and the flexibility of this model makes it possible to apply it for single-gate or p-type TFETs as well. To verify the model, the results are compared with TCAD Sentaurus simulations as well as measurement data. In both case model shows satisfying results.