Design & characterization of TWINE 80 bit IP core

This paper describes the RTL design and hardware characterization of 64 bit light weight block cipher TWINE-80. Twine-80 is an inherently small hardware design with lesser number of gates and low power consumption compared to many of its counterparts. Twine has 36 rounds which reduces the chance of attacks. Hardware prototyping of twine cipher is done on Spartane6 FPGA. Structure of Twine is simpler because of use of S-Box and XOR only. The use of non cyclic keys is known to provide faster diffusion and reduces attackable rounds.